research-article

Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis

Authors:

Ju Ho KimAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 24, Issue 3

Article No.: 28, Pages 1 - 22

https://doi.org/10.1145/3313798

Published: 05 April 2019 Publication History

Abstract

The semiconductor industry has accepted three-dimensional integrated circuits (3D ICs) as a possible solution to address speed and power management problems. In addition, 3D ICs have recently demonstrated a huge potential in reducing wire length and increasing the density of a chip. However, the growing density in chips such as TSV-based 3D ICs has brought the increased temperature on chip and temperature gradients depending on location. Thus, through silicon via (TSV)-based 3D clock tree synthesis (CTS) causes thermal problems leading to large clock skew. We propose a novel 3D symmetrical buffered clock tree synthesis considering thermal variation. First, <u>3D</u> abstract tree topology based on <u>n</u>earest-<u>n</u>eighbor selection with <u>m</u>edian cost (3D-NNM) is constructed by pairing sinks that have similar power consumption. Second, the layer assignment of internal nodes is determined for uniform TSV distribution. Third, in thermal-aware 3D deferred merging embedding (DME), the exact location of TSV is determined and wire routing/buffer insertion are performed after the thermal profile based on grid is obtained. The proposed method is verified using a 45nm process technology and utilized a predictive technology model (PTM) with HSPICE. It is also evaluated for the IBM benchmarks and ISPD’09 benchmarks with no blockages. In experimental result, we achieve on average 19% of clock skew reduction compared to existing thermal-aware 3D CTS. Therefore, thermal-aware 3D symmetrical buffered clock tree synthesis presented in this work is very efficient for circuit reliability.

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Cited By

Ran CZeng QCheng Y(2023)A Hierarchical Clock Network Synthesis Method for 3D Integrated Circuits with Obstacle Avoidance2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218627(345-350)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218627
Chi JZhu YZhu BZhao X(2022)A Charger Ripple Inhibition Strategy for Motor Train Unit Based on Compound Control2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)10.1109/ICEEMT56362.2022.9862609(159-163)Online publication date: 1-Jul-2022
https://doi.org/10.1109/ICEEMT56362.2022.9862609
Wang HLei QYang YLiu LZhao E(2022)A Clock Tree Synthesis Scheme Based On Flexible H-tree2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)10.1109/ICEEMT56362.2022.9862608(249-252)Online publication date: 1-Jul-2022
https://doi.org/10.1109/ICEEMT56362.2022.9862608

Index Terms

Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Clock-network synthesis

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 24, Issue 3

May 2019

266 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3319359

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2019 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 05 April 2019

Accepted: 01 January 2019

Revised: 01 November 2018

Received: 01 May 2018

Published in TODAES Volume 24, Issue 3

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IITP (Institute for Information & communications Technology Promotion)
IC Design Education Center (IDEC), Korea
Samsung Electronics Foundry team
MIST (Ministry of Science, ICT & Future Planning), Korea, under the National Program for Excellence in SW)

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Cited By

Ran CZeng QCheng Y(2023)A Hierarchical Clock Network Synthesis Method for 3D Integrated Circuits with Obstacle Avoidance2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218627(345-350)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218627
Chi JZhu YZhu BZhao X(2022)A Charger Ripple Inhibition Strategy for Motor Train Unit Based on Compound Control2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)10.1109/ICEEMT56362.2022.9862609(159-163)Online publication date: 1-Jul-2022
https://doi.org/10.1109/ICEEMT56362.2022.9862609
Wang HLei QYang YLiu LZhao E(2022)A Clock Tree Synthesis Scheme Based On Flexible H-tree2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)10.1109/ICEEMT56362.2022.9862608(249-252)Online publication date: 1-Jul-2022
https://doi.org/10.1109/ICEEMT56362.2022.9862608

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