FPGA

In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of ...

In order to narrow the speed and density gap between FPGAs and MPGAs we propose the development of “families” of FPGAs. Each FPGA family is targeted at a single maximum logic capacity, and consists of several “siblings”, or FPGAs of different yet ...

Area-IO provide a way to eliminate the IO bottleneck of field programmable logic devices (FPLDs) created the mismatch between the ability of perimeter bonds to provide IO and the propensity of logic to demand it. Whether the incorporation of area IO ...

TIERS is a new pipelined routing and scheduling algorithm implemented in a complete VirtualWire^TM compilation and synthesis system. TIERS is described and compared to prior work both analytically and quantitatively. TIERS improves system speed by as ...

One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning. We described the task of finding partition orderings, i.e., determining ...

Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmable gate array (FPGA) based reconfigurable coprocessor board (the Chameleon ...

The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DEC-...

A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when ...

Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, ...

In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization during the mapping process by computing min-cost min-height K-feasible cuts for critical nodes for depth minimization and ...

A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapath model is introduced that allows maximum flexibility in scheduling bus ...

We study the nominal delay minimization problem in LUT-based FPGA technology mapping, where interconnect delay is assumed proportional to net fannout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard ...

As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in order to implement memories ...

A novel field-programmable mixed-analog-digital array (FPMA) is proposed, which contains a field-programmable analog array, a field-programmable digital array, and a mixed-signal interface. This device is intended to be used for the rapid implementation ...

Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all ...

In this paper we examine three different problems related to FPGA placement: timing driven placement of a technology mapped circuit, timing driven reconfiguration for yield enhancement and fault tolerance in FPGAs and timing driven design re-engineering ...

This paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (FPGAs) such as those manufactured by Actel. The principles of this methodology are based on configuring the uncommitted ...

Recent research on FPGA partitioning has focussed on finding minimum cuts between partitions without regard to the routability of the partitioned subcircuits. In this paper we develop a spectral approach to multi-way partitioning in which the primary ...

This paper considers the problem of partitioning a circuit into a collection of subcircuits, such that each subcircuit is feasible for some device from an FPGA library, and the total cost of devices is minimized. We propose a three-phase heuristic that ...

Real-time video compression is a challenging subject for FPGA implementation because it typically has a large computational complexity and requires high data throughput. Previous implementations have used parallel banks of FPGAs or DSPs to meet these ...

During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. It is difficult to attach general-purpose logic analysers and in-circuit ...