MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

BIASING BJT:

In order to produce distortion-free output in amplifier circuits, the supply voltages and resistances in the
circuit must be suitably chosen. These voltages and resistances establish a set of dc voltage VCEQ and current
ICQ to operate the transistor in the active region. These voltages and currents are called quiescent values
which determine the operating point or Q-point for the transistor.

Biasing:
It is a process of giving proper supply voltages and resistances for obtaining the desired Q-point of a
transistor is called biasing. The circuits used for getting the desired and proper operating point are known as
biasing circuits.

The collector current for common-emitter amplifier is expressed by

Here the three variables hFE i.e β, IB and ICO are found to increase with temperature. For every 100 C rise in
temperature, ICO doubles itself. When ICO increases, IC increases significantly. This causes power dissipation
to increase and hence to make ICO increase. This will cause IC to increase further and the process becomes
cumulative which will lead to thermal runaway that will destroy the transistor. In addition, the quiescent
operating point can shift due to temperature changes and the transistor can be driven into the region of
saturation. The effect of β on the Q-point is shown in Figure below.

One more source of bias instability is to be

considered due to the variation of VBE with
temperature. VBE is about 0.6 V for a silicon
transistor and 0.2 V for a germanium transistor at
room temperature. As the temperature increases,
|VBE| decreases at the rate of 2.5 mV/0C for both
silicon and germanium transistors.

The transfer characteristic curve shifts to the left at

the rate of 2.5 mV/0C (at constant IC) for increasing
temperature and hence the operating point shifts
accordingly. To establish the operating point in the
active region, compensation techniques are needed.

DC Load Line:

Referring to the biasing circuit of Figure(a) shown below, the values of VCC and RC are fixed and IC and VCE
are dependent on RB.

Applying Kirchhoff’s voltage law to the collector circuit in Figure (a), we get

The straight line represented by AB in Figure (b) shown below is called the dc load line. The
coordinates of the end point A are obtained by substituting VCE= 0 in the above equation.
V V
Then I C = CC . Therefore, the coordinates of A are VCE =0 and I C = CC
RC RC
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

The coordinates of B are obtained by substituting IC= 0 in the above equation. Then VCE =VCC. Therefore
the coordinates of B are VCE =VCC and IC =0.Thus, the dc load line AB can be drawn if the values of RC and
VCC are known. As shown in Figure(b) just above, the optimum Q-point is located at the midpoint of the dc
load line AB between the saturation and cut off regions, i.e. Q is exactly midway between A and B. In order
to get faithful amplification, the Q-point must be well within the active region of the transistor.

Even though the Q-point is fixed properly, it is very important to ensure that the operating point remains
stable where it is originally fixed. If the Q-point shifts nearer to either A or B, the output voltage and current
get clipped, thereby output signal is distorted.

In practice, the Q-point tends to shift its position due to any or all of the following three main factors.

(a) Reverse saturation current, ICO , which doubles for every 100 C increase in temperature
(b) Base-emitter voltage, VBE , which decreases by 2.5 mV per 0 C
(c) Transistor current gain, β i.e. hFE which increases with temperature

Referring to Figure(a) just above, the base current IB is kept constant since IB is approximately equal to
VCC/RB. If the transistor is replaced by another one of the same type, one cannot ensure that the new
transistor will have identical parameters as that of the first one. Parameters such as β vary over a range. This
results in the variation of collector current IC for a given IB. Hence, in the output characteristics, the spacing
between the curves might increase or decrease which leads to the shifting of the Q-point to a location which
might be completely unsatisfactory.

AC Load Line:
After drawing the dc load line, the operating point Q is properly located at the centre of the dc load line. But
this operating point is chosen under zero input signal condition of the circuit. Hence, the ac load line should
also pass through the operating point Q. The effective ac load resistance, Rac, is the combination of RC
parallel to RL,

So the slope of the ac load line CQD will be (-1/Rac), To draw an ac load line, two end points, viz. maximum
VCE and maximum IC when the signal is applied are required.

By joining points C and D, ac load line CD is constructed. As RC >Rac, the dc l.oad line is less steep than the
ac load line.
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

When the signal is zero, we have the exact dc conditions. From the Figure(b) just above, it is clear that the
intersection of dc and ac load lines is the operating point Q.

Cut Off:
When the base current IB is equal to zero, then the region of working of transistor is known as the cut-off
region. Figure shown above left, a cut-off region in the output characteristics of a transistor.

Under cut-off conditions there is a very small amount of collector leakage current ICO, due mainly to
thermally produced carriers. In cut off, the base–emitter and the base–collector junctions are reverse biased.

Saturation:
In the output characteristics of a transistor, if the voltage between collector and emitter is increased then the
collector current increases, but there is a limiting value of VCE when the IC current saturates, that is, remains
almost constant. This happens for different values of IB creating the transistor working region is known as
the saturation region. At saturation, the Base–Collector junction becomes forward biased and IC can not
increase further. Figure shown just above right, the saturation region in the output characteristics of a
transistor.

Stability Factor (S):

The extent to which the collector current IC is stabilised with varying ICO is measured by a stability factor S.
It is defined as the rate of change of collector current IC with respect to the collector base leakage current
ICO, keeping both the current IB and the current gain β constant
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

The collector current for a CE amplifier is given by

…………………(A)

Differentiating the above equation with respect to IC , we get

…………………(1)

From this equation, it is clear that this factor S should be as small as possible to have better thermal stability.

Stability factors S’ and S”:

The stability factor S’ change of IC with VBE , keeping ICO and β constant

The stability factor S” is defined as the rate of change of IC with respect to β, keeping ICO and VBE constant.

METHODS OF TRANSISTOR BIASING:

The stability factors for some commonly used biasing circuits are discussed below.

1. Fixed Bias or Base Resistor Method:

A common emitter amplifier using fixed bias circuit is shown in Figure below The dc analysis of the circuit
yields the following equation.
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

Since this equation is independent of current IC,

dIB/dIC =0 and the stability factor given in Eq. (1)
reduces to

Since β is a large quantity, this is a very poor bias

stable circuit. Therefore, in practice, this circuit is not
used for biasing the base. The advantage of this
method are: (a) simplicity, (b) small number of
components required, and (c) if the supply voltage is
very large as compared to VBE of the transistor, then
the base current becomes largely independent of the
voltage VBE.

2. Emitter-Feedback Bias:

The emitter-feedback bias network shown in Figure

aside contains an emitter resistor for improving the
stability level over that of the fixed-bias
configuration. The analysis will be performed by
first examining the base-emitter loop and then using
the results to investigate the collector-emitter loop.

Base–Emitter Loop: Applying Kirchoff’s voltage

law for the base-feedback emitter loop, we get

………….(2)

Substituting Equation. (2) in Equation. (1), we get the stability factor as

MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

Note that the value of the stability factor S is always lower in emitter-feedback bias circuit than that of the
fixed bias circuit. Hence it is clear that a better thermal stability can be achieved in emitter-feedback bias
circuit than the fixed-bias circuit.

Collector-Emitter Loop:
Applying Kirchoff’s voltage law for the collector-emitter loop, we get

Substituting IE= IC , we have

VE is the voltage from emitter to ground and is determined by

The voltage from collector to ground can be determined from

The voltage at the base with respect to ground can be determined from

3. Collector-to-Base Bias or Collector-Feedback Bias:

A common emitter amplifier using collector-to-base bias circuit is shown in Figure below. This circuit is the
simplest way to provide some degree of stabilization to the amplifier operating point. If the collector current
IC tends to increase due to either increase in temperature or the transistor has been replaced by the one with a
higher β, the voltage drop across RC increases, thereby reducing the value of VCE. Therefore, IB decreases
which, in turn, compensates the increase in IC. Thus, greater stability is obtained. The loop equation for this
circuit is

……………….(3)
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

Substituting Equation. (3) into Equation. (1),

we get

As can be seen, this value of the stability factor

is smaller than the value obtained by fixed bias
circuit. Also, S can be made small and the
stability can be improved by making RB small
or RC large.

If RC is very small, then S =(β+ 1), i.e. stability

is very poor.

Hence, the value of RC must be quite large for good stabilization. Thus, collector-to-base bias arrangement is
not satisfactory for the amplifier circuits like transformer coupled amplifier where the dc load resistance in
collector circuit is very small. For such amplifiers, emitter bias or self bias will be the most satisfactory
transistor biasing for stabilization.

4. Collector-Emitter Feedback Bias:

Figure shown aside the collector-emitter feedback

bias circuit that can be obtained by applying both the
collector-feedback and emitter-feedback. Here
collector- feedback is provided by connecting a
resistance RB from the collector to the base and
emitter-feedback is provided by connection an
emitter resistance RE from the emitter to ground.
Both the feedbacks are used to control the collector
current IC and the base current IB in the opposite
direction to increase the stability as compared to the
previous biasing circuits.

Applying Kirchoff’s voltage law to the current, we

get

Since VBE is independent of IC,

Substituting the above equation in Equation. (1), we get

MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

From this, it is clear that the stability of the collector-emitter feedback bias circuit is always better than that
of the collector-feedback and emitter feedback circuits.

5. Voltage Divider Bias, Self Bias, or Emitter Bias:

A simple circuit used to establish a stable operating point is the self-biasing configuration. The self bias, also
called as emitter bias, or emitter resistor and potential divider circuit that can be used for low collector
resistance is shown in Figure below. The current in the emitter resistor RE causes a voltage drop which is in
the direction to reverse bias the emitter junction. For the transistor to remain in the active region, the base-
emitter junction has to be forward biased. The required base bias is obtained from the power supply through
the potential divider network of the resistances R1 and R2.

Use of Self-Bias Circuit as a Constant Current Circuit:

If IC tends to increase, say, due to increase in ICO with temperature, the current in RE increases. Hence, the
voltage drop across RE increases thereby decreasing the base current. As a result, IC is maintained almost
constant.

STABILIZATION FACTORS:

To Determine Stability Factor, S:

Applying Thevenin’s Theorem to the circuit of Figure shown above, for finding the base current, we have,

The loop equation around the base circuit can be written as

Differentiating this equation with respect to IC , we get,

MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

Substituting this equation in Equation. (1), we get

As can be seen, the value of S is equal to one if the ratio RB/RE is very small as compared to 1. As this ratio
becomes comparable to unity, and beyond towards infinity, the value of the stability factor goes on
increasing till S=1+ β.

This improvement in the stability up to a factor equal to 1 is achieved at the cost of power dissipation. To
improve the stability, the equivalent resistance RB must be decreased, forcing more current in the voltage
divider network of R1 and R2.

Often, to prevent the loss of gain due to the negative feedback, RE is shunted by a capacitor CE. The
capacitive reactance XCE must be equal to about one tenth of the value of the resistance RE at the lowest
operating frequency.

To Determine the Stability Factor S’:

The stability factor S’ is defined as the rate of change of IC with VBE, keeping ICO and β constant.

From Figure (b) of self bias circuit

…………..(4)

From Equation. (A), we have

……………….(5)

Substituting Equation. (5) in Equation. (4), we get

……………….(6)

Differentiating the above eq. w.r.t. VBE we get

MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

To Determine the Stability of S”:

The stability factor S” is defined as the rate of change of IC w.r.t. to β, keeping ICO and VBE constant.
Rearranging Equation. (6), we have

………..….(7)

Since β >>1, the numerator of the second term can be written as

………………...(8)

Substituting Equation. (8) in Equation. (7), we have

Differentiating the above equation w.r.t β and simplifying, we obtain

MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

BIASING THE FET:

For the proper functioning of a linear FET amplifier, it is necessary to maintain the operating point Q stable
in the central portion of the pinch off region. The Q-point should be independent of device parameter
variations and ambient temperature changes. This can be achieved by suitably selecting the gate to source
voltage (VGS) and drain current (ID) which is referred to as biasing.

Fixing the Q-point:

The Q-point, the quiescent point or operating point for a self-biased JFET is established by determining the
value of drain current ID for a desired value of gate-to-source voltage, VGS, or vice-versa. However, if the
data sheet of JFET includes a transfer characteristics curve, then the Q-point may be determined by using the
procedure given below.

1. Select a convenient value of drain current whose value is generally taken half of the maximum possible
value of drain current, IDSS , Then find the voltage drop across source resistor, RS , by

and the gate-to-source voltage from the equation

2. Plot the assumed value of drain current, ID, and the corresponding gate-to-source voltage, VGS, on the
transfer characteristics curve.

3. Draw a line through the plotted point and the origin. The point of intersection of the line and the curve
gives the desired Q-point. Then, read the co-ordinates of Q-point.

It is necessary to fix the Q-point near the mid-point of the transfer characteristic curve of a JFET. The mid-
point bias allows a maximum amount of drain current swing between the values of IDSS and the origin.

The following analytical method or graphical method can be used for the design of self bias circuit.

Analytical Method:
The values of the maximum drain current, IDSS , and the gate-to-source cut-off voltage, VGS (off ) are noted
down from the data sheets of JFET.

The value of the drain current is determined by

For example, if we select the gate-to-source voltage, VGS =VGS (off) /4 , then the value of the drain current
will be
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

Here, the drain current is slightly more than one-half of IDSS . But it will bias the JFET close to the mid-point
of the curve. The value of the drain resistor, RD, is selected in such a way that the drain voltage, VD, is equal
to half the drain supply voltage, RD. The value of gate resistor, RG, is chosen arbitrarily large, so that it
prevents loading on the driving stages.

Graphical Method:
A self-bias line is drawn such that it intersects the transfer characteristic curve near its mid-point gives the
required Q-point. Then the co-ordinates of the Q-point are obtained. The value of source resistance, RS, is
expressed by the ratio of gate-to-source voltage, VGS, to the drain current, ID.
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

Therefore, the source resistance is given by

However, a more accurate method is to draw a self-bias line through the coordinates of IDSS and VGS(off ) as
shown in Figure just above left of transfer characteristic. Then the point of intersection of self-bias line and
the transfer characteristic curve locates the Q-point. The value of the source resistor is expressed by the
relation

The value of drain resistor, RD, and the gate resistor, RG, are selected in the same way as discussed above for
the analytical method.

An FET may have a combination of self bias and fixed bias to provide stability of the quiescent drain current
against device and temperature variations.

Self-bias:

Figure as shown aside the self-bias circuit for an N-

channel FET. When the drain voltage VDD is applied,
a drain current ID flows even in the absence of gate
voltage (VG). The voltage drop across resistor RS
produced by the drain current is given by VS= IDRS.
This voltage drop reduces the gate to source reverse
voltage required for FET operation. The feedback
resistor Rs prevents any variation in
FET drain current.
The drain voltage, VD =VDD -IDRD

The drain-to-source voltage,

The gate-to-source voltage

When drain current increases, the voltage drop across RS increases. The increased voltage drop increases the
reverse gate to source voltage, which decreases the effective width of the channel and hence, reduces the
drain current. Now the reduced drain current decreases the gate to source voltage which, in turn, increases
the effective width of channel thereby increasing the value of drain current.

Voltage Divider Bias:

Figure (a) shown below the voltage divider bias circuit and its Thevenin’s equivalent is shown in Figure. (b).
Resistors R1 and R2 connected on the gate side forms a voltage divider.
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

The gate voltage,

The bias line satisfies the equation VGS =VGG- IDRS.

The drain to ground voltage, VD =VDD -IDRD

If the gate voltage VGG is very large as compared to gate to source VGS, the drain current is approximately
constant. In practice, the voltage divider bias is less effective with JFET than BJT.

This is because, in BJT, VBE ≈ 0.7 V (silicon) with only minor variations from one transistor to another. But
in a JFET, the VGS can vary several volts from one JFET to another.

Fixed Bias:

The FET device needs DC bias for setting the

gate to source voltage VGS to give desired drain-
current ID. For a JFET, the drain current is
limited by IDSS . Since the FET has a high input
impedance, it does not allow the gate current to
flow and the dc voltage of the gate set by a
voltage divider or a fixed battery is not affected
or loaded by the FET.

The fixed bias circuit for an N-Channel JFET

shown in Figure aside is obtained by using a
supply VGG.
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

This supply ensures that the gate is always negative with respect to source and no current flows through
resistor RG and gate terminal i.e. IG = 0. The VGG supply provides a voltage VGS to bias the N-channel JFET,

but no resulting current is drawn from the battery VGG. Resistor RG is included to allow any ac signal applied
through capacitor C to develop across RG. While any ac signal will develop across RG, the dc voltage drop
across RG is equal to IGRG which is equal to zero Volt.

Then, the gate to source voltage VGS is

The drain-source current ID is then fixed by the gate-source voltage. This current will cause a voltage drop
across the drain resistor RD and is given as

BIASING THE MOSFET:

Biasing of Enhancement MOSFET:

Figure shown aside the drain-to-gate bias circuit for

enhancement mode MOSFET. Here, the gate bias
voltage is

This circuit offers the dc stabilisation through the

feedback resistor Rf. However, the input resistance
is reduced because of Miller effect.

Miller's theorem states that if an impedance is

connected between the input and output nodes in
an amplifier, having a reference node N, then this
impedance can be replaced by two impedances, one
connected between the input and the reference node
and the other connected between the output and the
reference node.

The Miller effect accounts for the increase in the equivalent input capacitance of an inverting voltage
amplifier due to amplification of the effect of capacitance between the input and output terminals.

In a MOSFET-based switching circuit, the Miller effect limits switching speed because the drive circuit
has to charge and discharge the input capacitance in a reliable and low-loss way. In switching from On
to Off and back, the input capacitance must swap between these conditions.
MODULE-1: DIODE CIRCUITS AND TRANSISTOR AMPLIFIER

Also, the voltage divider biasing technique given for JFET can be used for the enhancement MOSFET.
Here, the dc stability is accomplished by the dc feedback through RS.

But the self-bias technique given for JFET cannot be used for establishing an operating point for the
enhancement MOSFET because the voltage drop across RS is in a direction to reverse-bias the gate and it
actually needs forward gate bias.

Figure shown aside an N-channel enhancement

mode MOSFET common source circuit with source
resistor. The gate voltage is

and the gate-to-source voltage is VGS= VDD -VG

Assuming that VGS >VTN and the MOSFET is

biased in the saturation region, the drain current is

Here the threshold voltage VTN and conduction

parameter KN are functions of temperature

The drain-to-source voltage is VDS =VDD -ID RD

If VDS > VDS(sat) =VGS -VTN, then the MOSFET is biased in the saturation region. If VDS< VDS (sat) =VGS -
VTN, then the MOSFET is biased in the nonsaturation region, and the drain current is given by

Biasing of Depletion MOSFET:

Both the self-bias technique and voltage divider bias circuit given for JFET can be used to establish an
operating point for the depletion mode MOSFET.