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- Bolado M, Posadas H, Castillo J, Huerta P, Sánchez P, Sánchez C, Fouren H and Blasco F Platform Based on Open-Source Cores for Industrial Applications Proceedings of the conference on Design, automation and test in Europe - Volume 2
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- Marwedel P and Sirocic B Multimedia components for the visualization of dynamic behavior in computer architectures Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture, (13-es)
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- Corno F and Squillero G An enhanced framework for microprocessor test-program generation Proceedings of the 6th European conference on Genetic programming, (307-316)
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- Haga S, Reeves N, Barua R and Marculescu D Dynamic Functional Unit Assignment for Low Power Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Corno F, Cumani G, Sonza Reorda M and Squillero G Fully Automatic Test Program Generation for Microprocessor Cores Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Agarwal A, Roy K and Vijaykumar T Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Zivkovic V, de Kock E, van der Wolf P and Deprettere E Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Lv T, Henkel J, Lekatsas H and Wolf W Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Paulin P, Pilkington C and Bensoudane E Network Processing Challenges and an Experimental NPU Platform Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
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- Ivanov L (2003). Hardware courses and the undergraduate computer science curriculum at small colleges, Journal of Computing Sciences in Colleges, 18:3, (177-184), Online publication date: 1-Feb-2003.
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- Moreno J and Moudgil M Scalable instruction-level parallelism through tree-instructions Proceedings of the 11th international conference on Supercomputing, (1-11)
- Cleary J, McWha J and Pearson M (1997). Timestamp representations for virtual sequences, ACM SIGSIM Simulation Digest, 27:1, (98-105), Online publication date: 1-Jul-1997.
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- Wilson K and Olukotun K Designing high bandwidth on-chip caches Proceedings of the 24th annual international symposium on Computer architecture, (121-132)
- Nahum E, Yates D, Kurose J and Towsley D (1997). Cache behavior of network protocols, ACM SIGMETRICS Performance Evaluation Review, 25:1, (169-180), Online publication date: 1-Jun-1997.
- Nahum E, Yates D, Kurose J and Towsley D Cache behavior of network protocols Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, (169-180)
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- O'Neil P and Quass D Improved query performance with variant indexes Proceedings of the 1997 ACM SIGMOD international conference on Management of data, (38-49)
- Bosselaers A, Govaerts R and Vandewalle J SHA Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques, (348-362)
- Fromm R, Perissakis S, Cardwell N, Kozyrakis C, McGaughy B, Patterson D, Anderson T and Yelick K (1997). The energy efficiency of IRAM architectures, ACM SIGARCH Computer Architecture News, 25:2, (327-337), Online publication date: 1-May-1997.
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- Rim K, Min B and Shin S (1997). An Architecture for High Availability Multi-user Systems, Computer Communications, 20:3, (197-205), Online publication date: 1-May-1997.
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- Wilken K and Kong T (1997). Concurrent Detection of Software and Hardware Data-Access Faults, IEEE Transactions on Computers, 46:4, (412-424), Online publication date: 1-Apr-1997.
- Herrmann D and Ernst R Register Synthesis for Speculative Computation Proceedings of the 1997 European conference on Design and Test
- Hertwig A and Wunderlich H Fast Controllers for Data Dominated Applications Proceedings of the 1997 European conference on Design and Test
- Sasaki T Memory Hierarchy Design for Jetpipeline Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
- Weicker R (1997). On the use of SPEC benchmarks in computer architecture research, ACM SIGARCH Computer Architecture News, 25:1, (19-22), Online publication date: 1-Mar-1997.
- Lam N, Chang S and Manwaring M Evaluating the performance of dynamic branch prediction schemes with BPSim Proceedings of the 1997 workshop on Computer architecture education, (9-es)
- Zhang Y and Adams G An interactive, visual simulator for the DLX pipeline Proceedings of the 1997 workshop on Computer architecture education, (2-es)
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- Saghir M, Chow P and Lee C (1996). Exploiting dual data-memory banks in digital signal processors, ACM SIGOPS Operating Systems Review, 30:5, (234-243), Online publication date: 1-Dec-1996.
- McKinley K and Temam O (1996). A quantitative analysis of loop nest locality, ACM SIGOPS Operating Systems Review, 30:5, (94-104), Online publication date: 1-Dec-1996.
- Olukotun K, Nayfeh B, Hammond L, Wilson K and Chang K (1996). The case for a single-chip multiprocessor, ACM SIGOPS Operating Systems Review, 30:5, (2-11), Online publication date: 1-Dec-1996.
- Machanick P (1996). The case for SRAM main memory, ACM SIGARCH Computer Architecture News, 24:5, (23-30), Online publication date: 1-Dec-1996.
- Mudge T (1996). Strategic directions in computer architecture, ACM Computing Surveys, 28:4, (671-678), Online publication date: 1-Dec-1996.
- Miguel J, Arruabarrena A, Beivide R and Gregorio J (1996). Assessing the Performance of the New IBM SP2 Communication Subsystem, IEEE Parallel & Distributed Technology: Systems & Technology, 4:4, (12-22), Online publication date: 1-Dec-1996.
- Snell Q and Gustafson J An analytical model of the HINT performance metric Proceedings of the 1996 ACM/IEEE conference on Supercomputing, (19-es)
- Tomiyama H and Yasuura H Size-Constrained Code Placement for Cache Miss Rate Reduction Proceedings of the 9th international symposium on System synthesis
- Finn G, Hotz S and Van Meter R (1996). The impact of a zero-scan Internet checksumming mechanism, ACM SIGCOMM Computer Communication Review, 26:5, (27-39), Online publication date: 1-Oct-1996.
- Peir J, Hsu W, Young H and Ong S Improving cache performance with balanced tag and data paths Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, (268-278)
- Saghir M, Chow P and Lee C Exploiting dual data-memory banks in digital signal processors Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, (234-243)
- McKinley K and Temam O A quantitative analysis of loop nest locality Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, (94-104)
- Olukotun K, Nayfeh B, Hammond L, Wilson K and Chang K The case for a single-chip multiprocessor Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, (2-11)
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- Driesen K and Hölzle U The direct cost of virtual function calls in C++ Proceedings of the 11th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, (306-323)
- Peir J, Hsu W, Young H and Ong S (1996). Improving cache performance with balanced tag and data paths, ACM SIGPLAN Notices, 31:9, (268-278), Online publication date: 1-Sep-1996.
- Saghir M, Chow P and Lee C (1996). Exploiting dual data-memory banks in digital signal processors, ACM SIGPLAN Notices, 31:9, (234-243), Online publication date: 1-Sep-1996.
- McKinley K and Temam O (1996). A quantitative analysis of loop nest locality, ACM SIGPLAN Notices, 31:9, (94-104), Online publication date: 1-Sep-1996.
- Olukotun K, Nayfeh B, Hammond L, Wilson K and Chang K (1996). The case for a single-chip multiprocessor, ACM SIGPLAN Notices, 31:9, (2-11), Online publication date: 1-Sep-1996.
- Belayneh S and Kaeli D (1996). A discussion on non-blocking/lockup-free caches, ACM SIGARCH Computer Architecture News, 24:4, (16), Online publication date: 1-Sep-1996.
- Gómez Pulido J, Sánchez Pérez J and Moreno Zamora J (1996). An educational tool for testing hierarchical multilevel caches, ACM SIGARCH Computer Architecture News, 24:4, (11-15), Online publication date: 1-Sep-1996.
- Vishkin U (1996). Can parallel algorithms enhance serial implementation?, Communications of the ACM, 39:9, (88-91), Online publication date: 1-Sep-1996.
- Ko U, Hill A and Balsara P Design techniques for high performance, energy efficient control logic Proceedings of the 1996 international symposium on Low power electronics and design, (97-100)
- Abdullah M (1996). hcc—a portable ANSI C compiler (with a code generator for the PowerPCs), ACM SIGPLAN Notices, 31:8, (52-59), Online publication date: 1-Aug-1996.
- Levitt J and Olukotun K A scalable formal verification methodology for pipelined microprocessors Proceedings of the 33rd annual Design Automation Conference, (558-563)
- Nayfeh B, Hammond L and Olukotun K Evaluation of design alternatives for a multiprocessor microprocessor Proceedings of the 23rd annual international symposium on Computer architecture, (67-77)
- Sechrest S, Lee C and Mudge T Correlation and aliasing in dynamic branch predictors Proceedings of the 23rd annual international symposium on Computer architecture, (22-32)
- Nayfeh B, Hammond L and Olukotun K (1996). Evaluation of design alternatives for a multiprocessor microprocessor, ACM SIGARCH Computer Architecture News, 24:2, (67-77), Online publication date: 1-May-1996.
- Sechrest S, Lee C and Mudge T (1996). Correlation and aliasing in dynamic branch predictors, ACM SIGARCH Computer Architecture News, 24:2, (22-32), Online publication date: 1-May-1996.
- Yang Y A Class of Interconnection Networks for Multicasting Proceedings of the 10th International Parallel Processing Symposium, (796-802)
- Sampogna A, Kaeli D, Green D, Silva M and Sniezek C Performance Modeling Using Object-Oriented Execution-Driven Simulation} Proceedings of the 29th Annual Simulation Symposium (SS '96)
- Kwon O, Park G and Han T (1996). A compiler optimization to reduce execution time of loop nest, ACM SIGARCH Computer Architecture News, 24:1, (6-11), Online publication date: 1-Mar-1996.
- McMahon S The capture, characterization, and performance analysis of Macintosh traces Proceedings of the 41st IEEE International Computer Conference
- McVoy L and Staelin C lmbench Proceedings of the 1996 annual conference on USENIX Annual Technical Conference, (23-23)
- Harrison L Examination of a memory access classification scheme for pointer-intensive and numeric programs Proceedings of the 10th international conference on Supercomputing, (133-140)
- Li Y and Chu W Using FPGA for computer architecture/organization education Proceedings of the 1996 workshop on Computer architecture education, (5-es)
- Torrellas J Computer architecture education at the University of Illinois Proceedings of the 1996 workshop on Computer architecture education, (2-es)
- Hammami O Real time aspects of cluster based caches Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications
- Afzal T (1995). Performance modeling using the Motorola PowerPC timing simulator, ACM SIGARCH Computer Architecture News, 23:4, (9-18), Online publication date: 1-Sep-1995.
- Phalke V A time invariant working set model for independent reference Proceedings of the 33rd annual ACM Southeast Conference, (156-164)
- Severson A and Nelson B (1995). Throughput in a counterflow pipeline processor, ACM SIGARCH Computer Architecture News, 23:1, (5-12), Online publication date: 1-Mar-1995.
- Mogul J, Bartlett J, Mayo R and Srivastava A Performance implications of multiple pointer sizes Proceedings of the USENIX 1995 Technical Conference Proceedings, (16-16)
- Kaeli D Combining object-oriented design and computer architecture into a single senior-level course Proceedings of the 1995 workshop on Computer architecture education, (11-es)
- Varma A, Kalampoukas L, Stiliadis D and Jacobson Q CPU design kit Proceedings of the 1995 workshop on Computer architecture education, (1-es)
- Kurlander S and Fischer C Zero-cost range splitting Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation, (257-265)
- Mogul J A better update policy Proceedings of the USENIX Summer 1994 Technical Conference on USENIX Summer 1994 Technical Conference - Volume 1, (7-7)
- Kurlander S and Fischer C (1994). Zero-cost range splitting, ACM SIGPLAN Notices, 29:6, (257-265), Online publication date: 1-Jun-1994.
- Quong R Expected I-cache miss rates via the gap model Proceedings of the 21st annual international symposium on Computer architecture, (372-383)
- Rodriguez B A minimal TTL processor for architecture exploration Proceedings of the 1994 ACM symposium on Applied computing, (338-340)
- Quong R (1994). Expected I-cache miss rates via the gap model, ACM SIGARCH Computer Architecture News, 22:2, (372-383), Online publication date: 1-Apr-1994.
- Ar S and Cai J Reliable benchmarks using numerical instability Proceedings of the fifth annual ACM-SIAM symposium on Discrete algorithms, (34-43)
- Chen J Memory behavior of an X11 window system Proceedings of the USENIX Winter 1994 Technical Conference on USENIX Winter 1994 Technical Conference, (16-16)
- Chen J and Bershad B The impact of operating system structure on memory system performance Proceedings of the fourteenth ACM symposium on Operating systems principles, (120-133)
- Diep T, Shen J and Phillip M EXPLORER Proceedings of the 26th annual international symposium on Microarchitecture, (225-235)
- Chen J and Bershad B (1993). The impact of operating system structure on memory system performance, ACM SIGOPS Operating Systems Review, 27:5, (120-133), Online publication date: 1-Dec-1993.
- Hill M, Larus J, Lebeck A, Talluri M and Wood D (1993). Wisconsin Architectural Research Tool Set, ACM SIGARCH Computer Architecture News, 21:4, (8-10), Online publication date: 1-Sep-1993.
- Kerns D and Eggers S Balanced scheduling Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation, (278-289)
- Kerns D and Eggers S (1993). Balanced scheduling, ACM SIGPLAN Notices, 28:6, (278-289), Online publication date: 1-Jun-1993.
- Bunda J, Fussell D, Athas W and Jenevein R 16-bit vs. 32-bit instructions for pipelined microprocessors Proceedings of the 20th annual international symposium on computer architecture, (237-246)
- Bunda J, Fussell D, Athas W and Jenevein R (1993). 16-bit vs. 32-bit instructions for pipelined microprocessors, ACM SIGARCH Computer Architecture News, 21:2, (237-246), Online publication date: 1-May-1993.
Index Terms
- Computer architecture (2nd ed.): a quantitative approach
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