We describe the design, characterization, and demonstration of a fully integrated single-photon avalanche diode (SPAD) imager for use in time-resolved fluorescence imaging. The imager consists of a 64-by-64 array of active SPAD pixels and... more
We describe the design, characterization, and demonstration of a fully integrated single-photon avalanche diode (SPAD) imager for use in time-resolved fluorescence imaging. The imager consists of a 64-by-64 array of active SPAD pixels and an on-chip time-to-digital converter (TDC) based on a delay-locked loop (DLL) and calibrated interpolators. The imager can perform both standard time-correlated single-photon counting (TCSPC) and an
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We present a hybrid CMOS based microsystem where magnetic actuation of microparticles is combined with integrated optical detection via Single Photon Avalanche Diodes (SPADs). The system's configuration permits the manipulation and... more
We present a hybrid CMOS based microsystem where magnetic actuation of microparticles is combined with integrated optical detection via Single Photon Avalanche Diodes (SPADs). The system's configuration permits the manipulation and detection of single magnetic particles having diameters of 1, 3 and 5 µm. We are able to show a size sensitivity of the particle detection, with a clear distinction
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A solid-state imager fabricated in CMOS technology is presented for depth information capture of arbitrary 3D objects with millimeter resolution. The system is based on an array of 32x32 pixels that independently measure the... more
A solid-state imager fabricated in CMOS technology is presented for depth information capture of arbitrary 3D objects with millimeter resolution. The system is based on an array of 32x32 pixels that independently measure the time-of-flight of a ray of light as it is reflected back from the objects in a scene. A single cone of pulsed laser light illuminates the
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ABSTRACT, The design and characterization of an imaging,sensor based on single,photon avalanche,diodes is presented. The sensor was fully integrated in a 0.35µm CMOS technology. The core of the imager,is an array of 4x112 pixels that... more
ABSTRACT, The design and characterization of an imaging,sensor based on single,photon avalanche,diodes is presented. The sensor was fully integrated in a 0.35µm CMOS technology. The core of the imager,is an array of 4x112 pixels that independently,and simultaneously detect the arrival time of photons,with picosecond,accuracy. A novel event-driven readout scheme,allows parallel column-wise and non-sequential, on-demand row-wise operation. Both time-correlated and time-uncorrelated
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This paper reports on our progress in developing multibeam two-photon fluorescence lifetime imaging microscopy (FLIM) based on time-correlated single-photon counting (TCSPC). The core of the system is a 2D array of solid-state... more
This paper reports on our progress in developing multibeam two-photon fluorescence lifetime imaging microscopy (FLIM) based on time-correlated single-photon counting (TCSPC). The core of the system is a 2D array of solid-state single-photon avalanche diodes (SPADs) operating simultaneously and at room temperature. To the best of our knowledge, this is the first solid-state demonstration of a two-photon multichannel FLIM system with a time resolution of 120ps.
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ABSTRACT We present a multi-channel digital Silicon photomultipliers (MD-SiPM) capable of detecting and timestamping up to 48 photons and we show the advantage of generating multiple timestamps in the context of positron emission... more
ABSTRACT We present a multi-channel digital Silicon photomultipliers (MD-SiPM) capable of detecting and timestamping up to 48 photons and we show the advantage of generating multiple timestamps in the context of positron emission tomography (PET). The MD-SiPM has a size of 800 μm × 800 μm and comprises 416 pixels. Three versions of the pixel exists with 1, 1.5, and 2 bit counters; the effects of different counting resolutions, dead time, and afterpulsing are also discussed.
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ABSTRACT In this paper, the reverse biasing and breakdown properties of the PureB diodes are investigated for different methods of processing the PureB anode window and the metal contacting. In particular, micron-sized devices are... more
ABSTRACT In this paper, the reverse biasing and breakdown properties of the PureB diodes are investigated for different methods of processing the PureB anode window and the metal contacting. In particular, micron-sized devices are examined in order to assess their suitability for use in dense imaging arrays that may require operation as avalanche photodiodes to obtain the necessary photosensitivity [6]. For such small devices implanted guard rings cannot be implemented without paying a penalty in fill-factor. At the same time it is also desirable to position the photosensitive area away from the oxide perimeter where permanent damage can be inflicted by high reverse currents. Therefore, a “virtual” guard, using an n-enhancement implantation in the central region of the diode is applied here.
Abstract Techniques are proposed for the routing of very high-frequency circuits. In this approach, performance sensitivities are used to derive a set of bounds on critical parasitics and to generate weights for a cost function which... more
Abstract Techniques are proposed for the routing of very high-frequency circuits. In this approach, performance sensitivities are used to derive a set of bounds on critical parasitics and to generate weights for a cost function which drives an area router. In addition to these bounds, design often requires that the length of interconnect lines be equal to predefined values, The routing scheme enforces both types of constraints in two phases. During the first phase all parasitic constraints are enforced on all nets. Equality constraints are enforced ...
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Almost every aspect of today's integrated electronics at-tempts to meet tougher performance budgets, while con-tinuously shrinking device features and power constraints. An aggressive reduction of feature size often... more
Almost every aspect of today's integrated electronics at-tempts to meet tougher performance budgets, while con-tinuously shrinking device features and power constraints. An aggressive reduction of feature size often results in lower signals, which causes lower noise margins, ...
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The problem of designing complex analog circuits is attacke dusing a hier archic altop-down, constr aint-driven design methodolo gy. In this methodolo gy, constraints are prop agate dautomatically from high-level specific ationsto physic... more
The problem of designing complex analog circuits is attacke dusing a hier archic altop-down, constr aint-driven design methodolo gy. In this methodolo gy, constraints are prop agate dautomatically from high-level specific ationsto physic aldesign through a sequence of gradual transformations. Constraint tr ansformation is a critic al step in the methodolo gy, sinc e it determines in lar ge p
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An avalanche photodiode array uses single-photon counting to perform time-of-flight range-finding on a scene uniformly hit by 100ps 250mW uncollimated laser pulses. The 32×32 pixel sensor, fabricated in a 0.8 μm CMOS process uses a... more
An avalanche photodiode array uses single-photon counting to perform time-of-flight range-finding on a scene uniformly hit by 100ps 250mW uncollimated laser pulses. The 32×32 pixel sensor, fabricated in a 0.8 μm CMOS process uses a microscanner package to enhance the effective resolution in the application to 64×64 pixels. The application achieves a measurement depth resolution of 1.3mm to a depth
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In this paper we report on a 32×32 optical imager based on single photon avalanche diodes integrated in CMOS technology. The maximum measured dynamic range is 120dB and the minimum noise equivalent intensity is 1.3 × 10-3 lx. The minimum... more
In this paper we report on a 32×32 optical imager based on single photon avalanche diodes integrated in CMOS technology. The maximum measured dynamic range is 120dB and the minimum noise equivalent intensity is 1.3 × 10-3 lx. The minimum integration time per pixel is 4 μs. The output of each pixel is digital, thereby requiring no complex read-out circuitry,
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We present a single-photon avalanche diode (SPAD) with a wide spectral range fabricated in an advanced 180 nm CMOS process. The realized SPAD achieves 20 % photon detection probability (PDP) for wavelengths ranging from 440 nm to 820 nm... more
We present a single-photon avalanche diode (SPAD) with a wide spectral range fabricated in an advanced 180 nm CMOS process. The realized SPAD achieves 20 % photon detection probability (PDP) for wavelengths ranging from 440 nm to 820 nm at an excess bias of 4 V, with 30 % PDP at wavelengths from 520 nm to 720 nm. Dark count rates (DCR) are at most 5 kHz, which is 30 Hz/μm2, at an excess bias of 4V when we measure 10 μm diameter active area structure. Afterpulsing probability, timing jitter, and temperature effects on DCR are also presented.
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ABSTRACT The Ge APD detectors are fabricated on Si by using a selective chemical-vapor deposition (CVD) epitaxial growth technique. A novel processing procedure was developed for the p+ Ge surface doping by a sequence of pure-Ga and... more
ABSTRACT The Ge APD detectors are fabricated on Si by using a selective chemical-vapor deposition (CVD) epitaxial growth technique. A novel processing procedure was developed for the p+ Ge surface doping by a sequence of pure-Ga and pure-B depositions (PureGaB). Then, PVD Al is used to contact the n-type Si and the anode of p+n Ge diode. Arrays of diodes with different areas, as large as 40×40 μm2, were fabricated. The resulting p+n diodes have exceptionally good IV characteristics with ideality factor of ~1.1 and low saturation currents. The devices can be fabricated with a range of breakdown voltages from a minimum of 9 V to a maximum of 13 V. They can be operated both in proportional and in Geiger mode, and exhibit relatively low dark counts, as low as 10 kHz at 1 V excess reverse bias. The dark current at 1 V reverse bias are as low as 2 pA and 20 pA for a 2×2 μm2 and 2×20 μm2 devices, respectively. Higher IR-induced current than that induced by visible light confirms the sensitivity of Ge photodiodes at room temperature. The 25% peak in Id/Iref at an IR-wavelength of 1100 nm in Geiger mode is measured for excess bias voltages of 3 V and 4 V, where Id refers to the photocurrent of the 2×20 μm2 device at different wavelengths, and Iref is the reference photodiode current. The timing response (Jitter) for the APD when exposed to a pulsed laser at 637 nm and 1 V excess bias is measured as 900 ps at full width of half maximum (FWHM).
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A 64-by-64-pixel CMOS single-photon avalanche diode (SPAD) imager for time-resolved fluorescence detection features actively quenched and reset pixels, allowing gated detection to eliminate pile-up nonlinearities common to most... more
A 64-by-64-pixel CMOS single-photon avalanche diode (SPAD) imager for time-resolved fluorescence detection features actively quenched and reset pixels, allowing gated detection to eliminate pile-up nonlinearities common to most time-correlated single-photon counting (TCSPC) approaches. Timing information is collected using an on-chip time-to-digital converter (TDC) based on a counter and a supply-regulated delay-locked loop (DLL).
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An optical imager is reported based on single photon avalanche diodes. The imager, fabricated in 0.8μm CMOS technology, consists of an array of 1024 pixels each with an area of 58μm×58μm for a total chip area of 2.5mm×2.8mm. The... more
An optical imager is reported based on single photon avalanche diodes. The imager, fabricated in 0.8μm CMOS technology, consists of an array of 1024 pixels each with an area of 58μm×58μm for a total chip area of 2.5mm×2.8mm. The architecture of the imager is reduced to a minimum since no A/D converter is required. Moreover, since the output of each
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A three-dimensional (3-D) imager is presented, capable of computing the depth map as well as the intensity scale of a given scene. The heart of the system is a two-dimensional array of single photon avalanche diodes fabricated in standard... more
A three-dimensional (3-D) imager is presented, capable of computing the depth map as well as the intensity scale of a given scene. The heart of the system is a two-dimensional array of single photon avalanche diodes fabricated in standard CMOS technology. The diodes exhibit low-noise equivalent-power high-dynamic range, and superior linearity. The 3-D imager achieves submillimetric precision at a depth-of-field
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A new approach to the layout of integrated circuits with multiplesymmetry axes is presented in this paper. When more than one symmetryis present, the usual approach to placement and compaction makesextensive use of hierarchy, which... more
A new approach to the layout of integrated circuits with multiplesymmetry axes is presented in this paper. When more than one symmetryis present, the usual approach to placement and compaction makesextensive use of hierarchy, which requires fixed positions for symmetryaxes. As a result, wiring and area optimizations are poor.The position of a virtual symmetry axis is variable, and dynamicallydefined by
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A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from... more
A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from high-level performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching
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... Cristiano Niclass, Student Member, IEEE, Alexis Rochas, Pierre-André Besse, and Edoardo Charbon, Member, IEEE ... for this behavior is that the peak electric field is located only in the diode's periphery, thus causing... more
... Cristiano Niclass, Student Member, IEEE, Alexis Rochas, Pierre-André Besse, and Edoardo Charbon, Member, IEEE ... for this behavior is that the peak electric field is located only in the diode's periphery, thus causing premature breakdown [8]. Biased just below , an avalanche ...
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New design paradigms based on the concept of system-on-chip are gradually replacing printed circuit board centric approaches. This trend is mainly due to two factors: far higher running speeds and greater miniaturization. The new... more
New design paradigms based on the concept of system-on-chip are gradually replacing printed circuit board centric approaches. This trend is mainly due to two factors: far higher running speeds and greater miniaturization. The new paradigms will accelerate design cycles, which in turn will force designers to reuse existing and acquire new circuits ready to be integrated. Such acceleration will be
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Poisson distributed spike trains are often used as the input to VLSI implementations of spiking neural networks. However, it can be difficult to generate large truly random spike distributions which can be easily applied as input to a... more
Poisson distributed spike trains are often used as the input to VLSI implementations of spiking neural networks. However, it can be difficult to generate large truly random spike distributions which can be easily applied as input to a chip. This work presents results recorded from an avalanche photo diode which demonstrates that it can be used to create a Poisson
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ABSTRACT
ABSTRACT Planetary surface exploration using laser induced breakdown spectroscopy (LIBS) to probe the composition of rocks has recently become a reality with the operation of the mast-mounted ChemCam instrument onboard the Curiosity... more
ABSTRACT Planetary surface exploration using laser induced breakdown spectroscopy (LIBS) to probe the composition of rocks has recently become a reality with the operation of the mast-mounted ChemCam instrument onboard the Curiosity rover. Following this success, Raman spectroscopy has steadily gained support as a means for using laser spectroscopy to identify not just composition but mineral phases, without the need for sample preparation. The RLS Raman Spectrometer is included on the payload for the ExoMars mission, and a Raman spectrometer has been included in an example strawman payload for NASA’s Mars 2020 mission. Raman spectroscopy has been identified by the community as a feasible means for pre-selection of samples on Mars for subsequent return to Earth. We present a next-generation instrument that builds on the widely used green-Raman technique to provide a means for performing Raman spectroscopy without the background noise that is often generated by fluorescence of minerals and organics. Microscopic Raman spectroscopy with a laser spot size smaller than the grains of interest can provide surface mapping of mineralogy while preserving morphology. A very small laser spot size 1 µm) is often necessary to identify minor phases that are often of greater interest than the matrix phases. In addition to the difficulties that can be posed by fine-grained material, fluorescence interference from the very same material is often problematic. This is particularly true for many of the minerals of interest that form in environments of aqueous alteration and can be highly fluorescent. We use time-resolved laser spectroscopy to eliminate fluorescence interference that can often make it difficult or impossible to obtain Raman spectra. We will discuss significant advances leading to the feasibility of a compact time-resolved spectrometer, including the development of a new solid-state detector capable of sub-ns time resolution. We will present results on planetary analog minerals to demonstrate the instrument performance including fluorescence rejection.
ABSTRACT Planetary surface exploration using laser induced breakdown spectroscopy (LIBS) to probe the composition of rocks has recently become a reality with the operation of the mast-mounted ChemCam instrument onboard the Curiosity... more
ABSTRACT Planetary surface exploration using laser induced breakdown spectroscopy (LIBS) to probe the composition of rocks has recently become a reality with the operation of the mast-mounted ChemCam instrument onboard the Curiosity rover. Following this success, Raman spectroscopy has steadily gained support as a means for using laser spectroscopy to identify not just composition but mineral phases, without the need for sample preparation. The RLS Raman Spectrometer is included on the payload for the ExoMars mission, and a Raman spectrometer has been included in an example strawman payload for NASA’s Mars 2020 mission. Raman spectroscopy has been identified by the community as a feasible means for pre-selection of samples on Mars for subsequent return to Earth. We present a next-generation instrument that builds on the widely used green-Raman technique to provide a means for performing Raman spectroscopy without the background noise that is often generated by fluorescence of minerals and organics. Microscopic Raman spectroscopy with a laser spot size smaller than the grains of interest can provide surface mapping of mineralogy while preserving morphology. A very small laser spot size 1 µm) is often necessary to identify minor phases that are often of greater interest than the matrix phases. In addition to the difficulties that can be posed by fine-grained material, fluorescence interference from the very same material is often problematic. This is particularly true for many of the minerals of interest that form in environments of aqueous alteration and can be highly fluorescent. We use time-resolved laser spectroscopy to eliminate fluorescence interference that can often make it difficult or impossible to obtain Raman spectra. We will discuss significant advances leading to the feasibility of a compact time-resolved spectrometer, including the development of a new solid-state detector capable of sub-ns time resolution. We will present results on planetary analog minerals to demonstrate the instrument performance including fluorescence rejection.
ABSTRACT In this work we present a substrate isolated single photon avalanche diode designed and fabricated in 180 nm CMOS technology. Substrate isolation is ensured by design to enable lower electrical crosstalk and to ease circuit... more
ABSTRACT In this work we present a substrate isolated single photon avalanche diode designed and fabricated in 180 nm CMOS technology. Substrate isolation is ensured by design to enable lower electrical crosstalk and to ease circuit integration. The presented device achieves wide spectral sensitivity enabling greater than 40% photon detection probability from 440 to 620 nm wavelength at 10 V excess bias. For a 12 μm active diameter, the dark count rate of the device is 17 Hz and 1.45 kHz at 2 and 10 V excess bias, respectively, while the after pulsing probability is less than 0.3% with 300 ns dead time at 10 V excess bias, and timing jitter was 70 ps (full width at half maximum) when using 405 nm wavelength laser.
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ABSTRACT This paper presents a digitally controlled charge pump (DCP) to supply high voltages, while ensuring temperature and load current independence of excess bias in cameras based on avalanche photodiodes. This is achieved through a... more
ABSTRACT This paper presents a digitally controlled charge pump (DCP) to supply high voltages, while ensuring temperature and load current independence of excess bias in cameras based on avalanche photodiodes. This is achieved through a single-photon avalanche diode (SPAD) based monitoring mechanism that continuously reconfigures the DCP using a feedback loop to compensate breakdown voltage variations by temperature and load current in real time. The sensitivity of the SPADs, or photon detection probability (PDP), is maintained to within 1.9% when the temperature shifts from 28°C to 65°C and the load current changes from 0 μA to 100 μA.
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ABSTRACT This paper presents a compresensive analysis of timing resolution for a digital silicon photomultiplier (D-SiPM) using a SPICE simulator. Generally, digital silicon photomultipliers (D-SiPMs) have a full-width-half-maximum (FWHM)... more
ABSTRACT This paper presents a compresensive analysis of timing resolution for a digital silicon photomultiplier (D-SiPM) using a SPICE simulator. Generally, digital silicon photomultipliers (D-SiPMs) have a full-width-half-maximum (FWHM) single-photon timing resolution (SPTR) of more than 100 ps, often of several hundreds picoseconds. This is primarily due to detector jitter, circuit noise, and routing skew. Circuit noise and skew, in turn, strongly depend on the SiPM design; this dependency has been investigated by varying transistor size and transistor channel length, wire resistance, and capacitance. The scalability of the method has been validated by considering D-SiPMs of different sizes and with a variety of signal distribution architectures.
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We present an array of 128times128 highly miniaturized SPAD (single-photon avalanche diodes) pixels with a bank of 32 time-to-digital converters (TDCs) on chip. A decoder selects a 128-pixel row. Every group of 4 pixels in the row shares... more
We present an array of 128times128 highly miniaturized SPAD (single-photon avalanche diodes) pixels with a bank of 32 time-to-digital converters (TDCs) on chip. A decoder selects a 128-pixel row. Every group of 4 pixels in the row shares a TDC based on an event-driven mechanism. As a result, row-wise parallel acquisition is obtained with a low number of TDCs. Because
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ABSTRACT An in vivo hybrid imaging system for simultaneous magnetic resonance and fluorescence molecular tomography imaging, providing adequate spatial resolution and quantification capabilities, is described. Imaging performance in vivo... more
ABSTRACT An in vivo hybrid imaging system for simultaneous magnetic resonance and fluorescence molecular tomography imaging, providing adequate spatial resolution and quantification capabilities, is described. Imaging performance in vivo is demonstrated using a murine tumor model.
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ABSTRACT In this paper, we present an array of 160x128 pixels capable of detecting the ToA of single photons, implemented in 0.13μm CMOS technology. The sensor is partitioned into 4 identical quadrants that are served by a balanced clock... more
ABSTRACT In this paper, we present an array of 160x128 pixels capable of detecting the ToA of single photons, implemented in 0.13μm CMOS technology. The sensor is partitioned into 4 identical quadrants that are served by a balanced clock tree so as to minimize skews and to ensure the fastest possible readout process. The pixels in the rows are read out in rolling shutter mode in two directions (top and bottom) simultaneously. The 10b content of each pixel is thus transferred to the exterior of the chip via 320 independent serializers, 2 for each column, working in parallel at a maxi mum rate of 160Mb/s, thus enabling in principle the readout of a complete frame in 4μs. In our implementation the frame rate is actually lower, due to current lim itations in the readout firmware. The region-of-interest (Rol) is programmable, via vertical and horizontal registers that select which rows and columns are read out.
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A Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion is implemented in a 130-nm CMOS imaging technology. The proposed module is conceived for Single-Photon Avalanche Diode imagers and can operate both as a TAC or... more
A Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion is implemented in a 130-nm CMOS imaging technology. The proposed module is conceived for Single-Photon Avalanche Diode imagers and can operate both as a TAC or as an analog counter, thus allowing both time-correlated or time-uncorrelated imaging operation. A single-ramp, 8-bit ADC with two memory banks to allow high-speed, time-interleaved operation is
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Although microfluidics and microarray technologies are revolutionizing the throughput, sensitivity and cost in many areas of biodiagnostics, they are still reliant on bulky and expensive fluorescence analysis instrumentation. Conventional... more
Although microfluidics and microarray technologies are revolutionizing the throughput, sensitivity and cost in many areas of biodiagnostics, they are still reliant on bulky and expensive fluorescence analysis instrumentation. Conventional fluorescence intensity measurements are prone to misinterpretation due to illumination and fluorophore concentration non-uniformities. Thus, there is a growing interest in time-resolved fluorescence detection, whereby the characteristic fluorescence decay time-constant (or lifetime) in response to an impulse excitation source is measured.
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A 0.35mum CMOS camera uses 128 single-photon avalanche diodes to simultaneously detect 128 photon times-of-arrival, which are then translated onto pulses that are independently injected into a timing-preserving delay line, implemented... more
A 0.35mum CMOS camera uses 128 single-photon avalanche diodes to simultaneously detect 128 photon times-of-arrival, which are then translated onto pulses that are independently injected into a timing-preserving delay line, implemented along the sensor's column. With this design, an overall timing accuracy of 145ps (worst case) is achieved, which enables high-precision time-correlated single-photon counting for state-of-the-art physics, bio-molecular, and medical imaging applications.
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Single Photon Avalanche Diodes (SPADs) have been used for photon counting since the 1960s, but only in the recent decade multi-pixel structures based on SPAD—arrays and silicon photomultipliers have been developed. These devices are... more
Single Photon Avalanche Diodes (SPADs) have been used for photon counting since the 1960s, but only in the recent decade multi-pixel structures based on SPAD—arrays and silicon photomultipliers have been developed. These devices are finding more and more applications in many fields, where detection of light at the level of a single photon is needed. Due to their exclusive properties
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ABSTRACT We report the first fully integrated single photon avalanche diode array fabricated in 0.35μm CMOS technology. At 25μm, the pixel pitch achieved by this design is the smallest ever reported. Thanks to the level of miniaturization... more
ABSTRACT We report the first fully integrated single photon avalanche diode array fabricated in 0.35μm CMOS technology. At 25μm, the pixel pitch achieved by this design is the smallest ever reported. Thanks to the level of miniaturization enabled by this design, we were able to build the largest single photon streak camera ever built in any technology, thus proving the scalability of the technology. Applications requiring low noise, high dynamic range, and/or picosecond timing accuracies are the prime candidates of this technology. Examples include bio-imaging at cellular and molecular level, fast optical imaging, single photon telecommunications, 3D cameras, optical rangefinders, LIDAR, and low light level imagers.
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To accelerate the design cycle for analog circuits and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. In this paper we present a design which demonstrates the two principal advantages that this... more
To accelerate the design cycle for analog circuits and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. In this paper we present a design which demonstrates the two principal advantages that this methodology provides- a high probability for first silicon which meets all specifications and fast design times. We examine the design of three different 10-bit digital-to-analog (D/A)
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We present the architecture and three applications of the largest resolution image sensor based on single-photon avalanche diodes (SPADs) published to date. The sensor, fabricated in a high-voltage CMOS process, has a resolution of 512 ×... more
We present the architecture and three applications of the largest resolution image sensor based on single-photon avalanche diodes (SPADs) published to date. The sensor, fabricated in a high-voltage CMOS process, has a resolution of 512 × 128 pixels and a pitch of 24 μm. The fill-factor of 5% can be increased to 30% with the use of microlenses. For precise control of the exposure and for time-resolved imaging, we use fast global gating signals to define exposure windows as small as 4 ns. The uniformity of the gate edges location is ∼140 ps (FWHM) over the whole array, while in-pixel digital counting enables frame rates as high as 156 kfps. Currently, our camera is used as a highly sensitive sensor with high temporal resolution, for applications ranging from fluorescence lifetime measurements to fluorescence correlation spectroscopy and generation of true random numbers.
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ABSTRACT We present a monolithic silicon chip comprising a matrix of 84 single photon avalanche diodes (SPADs) to detect and discriminate fluorescent beads or fluorescently labeled single cells in a polydimethyl(-siloxane) (PDMS)... more
ABSTRACT We present a monolithic silicon chip comprising a matrix of 84 single photon avalanche diodes (SPADs) to detect and discriminate fluorescent beads or fluorescently labeled single cells in a polydimethyl(-siloxane) (PDMS) cartridge that is positioned on top of the chip. Our detection is based on the different photon count when either a fluorescent or non-fluorescent bead or cell is present above a SPAD, due to the additional photons emitted from a fluorescent object. Our technique allows microscope-less fluorescence detection and permits easy exchange of the disposable microfluidic cartridge. We first demonstrate the working principle of our device by counting and discriminating fluorescent from non-fluorescent 3, 6 and 10 μm magnetic beads, which are commonly used as versatile mobile carriers for separating a target analyte from a matrix via magnetic forces in microfluidic lab-on-a-chip systems. We then apply our system to count and discriminate fluorescently-labeled MCF-7 breast cancer cells from unlabeled Jurkat cells mixed in a phosphate buffer saline (PBS) solution. Our device is robust and does not need complex microfluidic handling to achieve cell count without the need of external fluorescence detection bulky equipment.
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We present an optimization technique utilizing order statistics with a multichannel digital silicon photomultiplier (MD-SiPM) for timing measurements. Accurate timing measurements are required by 3D rangefinding and time-of-flight... more
We present an optimization technique utilizing order statistics with a multichannel digital silicon photomultiplier (MD-SiPM) for timing measurements. Accurate timing measurements are required by 3D rangefinding and time-of-flight positron emission tomography, to name a few applications. We have demonstrated the ability of the MD-SiPM to detect multiple photons, and we verified the advantage of detecting multiple photons assuming incoming photons follow a Gaussian distribution. We have also shown the advantage of utilizing multiple timestamps for estimating time-of-arrivals more accurately. This estimation technique can be widely available in various applications, which have a certain probability density function of incoming photons, such as a scintillator or a laser source.
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Research Interests: Optics, Fluorescence Microscopy, Semiconductors, Neurospora crassa, Fluorescence Lifetime, and 14 moreComputer Systems, Time Resolved, Real Time, Optical physics, Image Enhancement, Photons, Reproducibility of Results, Extraction Method, Sensitivity and Specificity, Equipment Design, Equipment Failure Analysis, Electrical And Electronic Engineering, Fluorescence Lifetime Imaging, and Dynamic Range
Research Interests: Algorithms, Fluorescence Microscopy, Semiconductors, X-ray imaging, Fluorescence Correlation Spectroscopy, and 16 moreX Rays, Computer Simulation, Time of Flight, Three Dimensional Imaging, Electromagnetic Fields, Time Resolved, Optical physics, Room Temperature, Photons, Impact Ionization, Optics and Photonics, Reproducibility of Results, Detection Probability, Electric Field, Electrical And Electronic Engineering, and Fluorescence Lifetime Imaging
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A high-speed and hardware-only algorithm using a center of mass method has been proposed for single-detector fluorescence lifetime sensing applications. This algorithm is now implemented on a field programmable gate array to provide fast... more
A high-speed and hardware-only algorithm using a center of mass method has been proposed for single-detector fluorescence lifetime sensing applications. This algorithm is now implemented on a field programmable gate array to provide fast lifetime estimates from a 32 × 32 low dark count 0.13 μm complementary metal-oxide-semiconductor single-photon avalanche diode (SPAD) plus time-to-digital converter array. A simple look-up table is included to enhance the lifetime resolvability range and photon economics, making it comparable to the commonly used least-square method and maximum-likelihood estimation based software. To demonstrate its performance, a widefield microscope was adapted to accommodate the SPAD array and image different test samples. Fluorescence lifetime imaging microscopy on fluorescent beads in Rhodamine 6G at a frame rate of 50 fps is also shown.
Research Interests: Algorithms, Biomedical Engineering, Fluorescence Microscopy, Semiconductors, Digital Circuits, and 15 moreBiomedical Imaging, Fluorescence Lifetime, Biomedical Optics, Micro Electro Mechanical System, Look up Table, Field Programmable Gate Array, Optical physics, High Speed, Optometry and Ophthalmology, Photons, Microspheres, Equipment Design, Center of Mass, Fluorescence Lifetime Imaging, and Least Square Method
Abstract A tool named SPARCS-A for compaction of integrated circuits with analogue constraints is presented. the approach is structured in two steps. First a robust and efficient constraint graph compaction algorithm produces a compacted... more
Abstract A tool named SPARCS-A for compaction of integrated circuits with analogue constraints is presented. the approach is structured in two steps. First a robust and efficient constraint graph compaction algorithm produces a compacted layout quickly, where parasitics are controlled so as to guarantee that the performance constraints are met. Next the layout produced by the first step is fed into a linear programming (LP) solver which enforces symmetries and performs global interconnect length minimization. the ...
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In a top-down design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take... more
In a top-down design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into subtask requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach in industrial-strength applications
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Research Interests: Engineering, Magnetic Resonance Imaging, Fluorescence Microscopy, Semiconductors, Optical Tomography, and 21 moreOptical coherence tomography, Optical Imaging, Biomedical Imaging, Transducers, Mice, Photometry, Animals, Fluorescence Imaging, Rats, Optical fiber, Photons, Colon cancer, Miniaturization, Reproducibility of Results, Small Animal PET Imaging, Light Propagation, Sensitivity and Specificity, High Sensitivity, Equipment Design, Equipment Failure Analysis, and Surface Wave
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Abstract The authors present an extractor, INDEX, designed to extract superconducting circuits from layout. The inductances of the superconducting lines are calculated by a set of analytical models. These self-and mutual-inductance models... more
Abstract The authors present an extractor, INDEX, designed to extract superconducting circuits from layout. The inductances of the superconducting lines are calculated by a set of analytical models. These self-and mutual-inductance models are generated from a series of numerical simulations and a linear programming curve-fitting. INDEX is based on the MAGIC layout system. INDEX has been tested on a number of cases with good results. A two-junction superconducting quantum interference device (SQUID) was used as one test case
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Watermarking is one of several techniques available today to deter copyright infringement in electronic systems. The technique consists of implanting indelible stamps in the... more
Watermarking is one of several techniques available today to deter copyright infringement in electronic systems. The technique consists of implanting indelible stamps in the circuit's inner structure, while not disrupting its functionality nor degrading its performance significantly. In this paper, a novel method is proposed for the creation of watermarks in regular sequential functions. This is an important class of
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... Cristiano Niclass, Student Member, IEEE, Alexis Rochas, Pierre-André Besse, and Edoardo Charbon, Member, IEEE ... for this behavior is that the peak electric field is located only in the diode's periphery, thus causing... more
... Cristiano Niclass, Student Member, IEEE, Alexis Rochas, Pierre-André Besse, and Edoardo Charbon, Member, IEEE ... for this behavior is that the peak electric field is located only in the diode's periphery, thus causing premature breakdown [8]. Biased just below , an avalanche ...
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Waveguide structure for propagating a surface plasmon polariton,comprising an inter- metal plasmonic waveguide (1). The waveguide structure has two metal strip like structures (2, 3)positioned parallel to each other and an isolating... more
Waveguide structure for propagating a surface plasmon polariton,comprising an inter- metal plasmonic waveguide (1). The waveguide structure has two metal strip like structures (2, 3)positioned parallel to each other and an isolating material structure (4) positioned between the two metal strip like structures(2, 3). The two metal strip like structures (2, 3) are positioned at a fixed distance (d) from
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ABSTRACT This paper presents a digital silicon photomultiplier based on column-parallel time-to-digital converter (TDC), so as to improve the time resolution of single-photon detection. By reducing the number of pixels per TDC, the... more
ABSTRACT This paper presents a digital silicon photomultiplier based on column-parallel time-to-digital converter (TDC), so as to improve the time resolution of single-photon detection. By reducing the number of pixels per TDC, the pixel-to-pixel skew is reduced. We achieved 264 ps FWHM time resolution of single-photon detection using a 48-fold column-parallel TDC with a temporal resolution of 51.8ps (LSB), fully integrated in standard CMOS technology. The potential for multi-photon detection is discussed in the paper with a 48-column-parallel TDC configuration.
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... Spartan-3 board Clock input ... decoder is used to serialize the data coming from the array onto two serial channels via the 16bit shift resistor. ... Mitani, H. Minami, T. Noda, K. Sagawa T. Tokuda, and J. Ohta, “Complementary Metal... more
... Spartan-3 board Clock input ... decoder is used to serialize the data coming from the array onto two serial channels via the 16bit shift resistor. ... Mitani, H. Minami, T. Noda, K. Sagawa T. Tokuda, and J. Ohta, “Complementary Metal Oxide Semiconductor Based Multimodal Sensor for ...
A solid-state imager fabricated in CMOS technology is presented for depth information capture of arbitrary 3D objects with millimeter resolution. The system is based on an array of 32x32 pixels that independently measure the... more
A solid-state imager fabricated in CMOS technology is presented for depth information capture of arbitrary 3D objects with millimeter resolution. The system is based on an array of 32x32 pixels that independently measure the time-of-flight of a ray of light as it is reflected back from the objects in a scene. A single cone of pulsed laser light illuminates the scene, thus no complex mechanical scanning is required. Millimetric depth accuracies can be reached thanks to the rangefinder's optical detectors that enable picosecond time discrimination. The detectors, based on a single photon avalanche diode operating in Geiger mode, utilize avalanche multiplication to enhance light detection. Optical power requirements on the light source can therefore be significantly relaxed. A number of standard performance measurements, conducted on the imager, are discussed in this paper. The D imaging system was also tested on real 3D subjects demonstrating the suitability of the approach.
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In this paper a method is presented for automatically generating a parameterized model of integrated inductors accounting for geometry and substrate effects. A multiparameter Krylov-subspace based moment matching method is used to reduce... more
In this paper a method is presented for automatically generating a parameterized model of integrated inductors accounting for geometry and substrate effects. A multiparameter Krylov-subspace based moment matching method is used to reduce the ...
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I. INTRODUCTION HENEVER the charge transport through a solid-state device is controlled by the charging and discharging of a single defect, it gives rise to a discrete switching of the current, called burst or popcorn noise, or more often... more
I. INTRODUCTION HENEVER the charge transport through a solid-state device is controlled by the charging and discharging of a single defect, it gives rise to a discrete switching of the current, called burst or popcorn noise, or more often RTS [1]. Although RTS is important ...
A methodology is presented for generating compact models of substrate noise injection in complex logic networks. For a given gate library, the injection patterns associated with a gate and an input transition scheme are accurately... more
A methodology is presented for generating compact models of substrate noise injection in complex logic networks. For a given gate library, the injection patterns associated with a gate and an input transition scheme are accurately evaluated using device-level simulation. Assuming spatial independence of all noise generating devices, the cumulative switching noise resulting from all injection patterns is efficiently computed using a gate-level event-driven simulator. The resulting injected signal is then sampled and ...
FOREWORDEmbedded System Cost Optimization via Data Path Width AdjustmentFast Scheduling and Allocation Algorithms for Entropy CODECAn lterative Improvement Method for State Minimization of Incompletely Specified Finite State MachinesMinimization of AND-OR-EXOR Three-Level Networks with AND Gate S...more
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In this paper a semi-analytical method is presented to model the electron diffusion in an arbitrary p-substrate. The approach is based on the Green function tecnique. The Green function is derived over a multilayer substrate by solving... more
In this paper a semi-analytical method is presented to model the electron diffusion in an arbitrary p-substrate. The approach is based on the Green function tecnique. The Green function is derived over a multilayer substrate by solving the diffusion equations analyti- cally in the z coordinate and numerically in the x and y coordi- nates. Using this technique, the substrate
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In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of... more
In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.
In a constraint-driven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in... more
In a constraint-driven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to non-deterministic process variations. ...
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Techniques are presented for simultaneous placement and module optimization for analog ICs. An algorithmic approach to module generation provides alternative sets of modules, optimized with respect to performance but with different... more
Techniques are presented for simultaneous placement and module optimization for analog ICs. An algorithmic approach to module generation provides alternative sets of modules, optimized with respect to performance but with different trade-offs among area, parasitics and matching. A simulated annealing algorithm performs the placement, selecting among the available configurations the one that best fulfils all performance and geometric requirements. Compared to standard approaches, the flexibility of placement is ...
A number of methods are presented for highly efficient calculation of substrate current transport. A three-dimensional Green Function based substrate representation, in combination with the use of the Fast Fourier Transform, significantly... more
A number of methods are presented for highly efficient calculation of substrate current transport. A three-dimensional Green Function based substrate representation, in combination with the use of the Fast Fourier Transform, significantly speeds up the computation of sensitivities with respect to all parameters associated with a given architecture. Substrate sensitivity analysis is used in a number of physical optimization tools, such as placement and trend analysis for the estimation of the impact of technology ...
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A new approach to the layout of integrated circuits with multiple symmetry axes is presented in this paper. When more than one symmetry is present, the usual approach to placement and compaction makes extensive use of hierarchy, which... more
A new approach to the layout of integrated circuits with multiple symmetry axes is presented in this paper. When more than one symmetry is present, the usual approach to placement and compaction makes extensive use of hierarchy, which requires xed positions for symmetry axes. As a result, wiring and area optimizations are poor. The position of a virtual symmetry axis is variable, and dynamically de ned by the center of a group of symmetric modules and wires called cluster. Virtual symmetry axes have been ...
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An ejjicient approach to the symbolic compaction of analog integrated civcuits is presented. A jast graph-based algorithm peT-jorms a preliminary compaction taking into account a set of basic spacing constraints. The obtained... more
An ejjicient approach to the symbolic compaction of analog integrated civcuits is presented. A jast graph-based algorithm peT-jorms a preliminary compaction taking into account a set of basic spacing constraints. The obtained configuration provides the starting point for a linear program, which optimizes the layout introducing multiple device and wire symmetry constraints. The efficiency and robustness of this technique allows the use of our compactor for very complex analog cinxits with multiple symmetries and other ...
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A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from... more
A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from high-level performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to ...